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Multichannel 25 Gb/s low-power driver and transimpedance amplifier integrated circuits for 100 Gb/s optical links

机译:多通道25 Gb / s低功耗驱动器和跨阻抗放大器集成电路,用于100 Gb / s光链路

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摘要

Highly integrated electronic driver and receiver ICs with low-power consumption are essential for the development of cost-effective multichannel fiber-optic transceivers with small form factor. This paper presents the latest results of a two-channel 28 Gb/s driver array for optical duobinary modulation and a four-channel 25 Gb/s TIA array suited for both NRZ and optical duobinary detection. This paper demonstrated that 28 Gb/s duobinary signals can be efficiently generated on chip with a delay-and-add digital filter and that the driver power consumption can be significantly reduced by optimizing the drive impedance well above 50 Omega, without degrading the signal quality. To the best of our knowledge, this is the fastest modulator driver with on-chip duobinary encoding and precoding, consuming only 652 mW per channel at a differential output swing of 6 Vpp. The 4 x 25 Gb/s TIA shows a good sensitivity of - 10.3 dBm average optical input power at 25 Gb/s for PRBS 2(31) -1 and low power consumption of 77 mW per channel. Both ICs were developed in a 130 nm SiGe BiCMOS process.
机译:具有低功耗的高度集成的电子驱动器和接收器IC对于开发经济高效的小尺寸多通道光纤收发器至关重要。本文介绍了适用于光双二进制调制的两通道28 Gb / s驱动器阵列和适用于NRZ和光双二进制检测的四通道25 Gb / s TIA阵列的最新结果。本文证明了使用延迟加法数字滤波器可以在芯片上高效地产生28 Gb / s双二进制信号,并且通过优化远高于50 Omega的驱动阻抗可以显着降低驱动器功耗,而不会降低信号质量。据我们所知,这是最快的调制器驱动器,具有片上双二进制编码和预编码功能,在6 Vpp的差分输出摆幅下,每个通道仅消耗652 mW。对于PRBS 2(31)-1,4 x 25 Gb / s TIA在25 Gb / s时显示出-10.3 dBm的平均光输入功率的良好灵敏度,每通道77 mW的低功耗。两种IC均采用130 nm SiGe BiCMOS工艺开发。

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